The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, is neither expressly nor impliedly admitted as prior art against the present disclosure.
Data error rates in traditional flash memory devices depend on the duration of time the data is retained in the memory as well as the number of program-erase (PE) cycles of the page where the data resides and many other factors. Traditional systems use error correction code circuitries (FCC) and decoding engines to detect/correct data errors encountered when reading the data from the flash memory devices. In addition, because the amount of: errors in the data (i.e., bit error rate or signal to noise ratio) could vary widely between different data sets that are read from memory, the type of decoding engine that is needed to decode a given data set is unknown when the data is read.
To address these uncertainties, traditional systems first attempt to decode the data with the least complex decoding technique (i.e., a technique based on hard decisions). If the least complex decoding technique decodes the data unsuccessfully, these systems then attempt to decode the same data with a more complex decoding technique (i.e., using more iterations than the less complex decoding technique). Although the data in these systems is eventually successfully decoded, the decoding process typically requires many decoding attempts to decode one data set and therefore lacks efficiency (i.e., wastes resources, consumes a large amount of power and increases decoding latency by taking more time to decode).